• Integration Software in the loop and hardware in the loop for SDV architectures

The transition to the software-defined vehicle is changing the way in which automotive software is developed - and tested. Validating ECUs in vehicle prototypes and Hardware-in-the-loop (HIL) simulators, as is often the case today, is no longer sufficient. Software-in-the-loop (SIL) as a purely software-based test environment is playing an increasingly important role and will be crucial to shorten the time-to-market of new functionalities. Nevertheless, traditional test environments will remain important. A holistic validation strategy must therefore consider all steps: from pure functional tests to the validation of the entire vehicle architecture. And it must use the test platforms that are suitable for the validation task in question. SIL and HIL must therefore be highly integrated and interact smoothly. The presentation shows how these challenges can be tackled.

• Architecture native accelerated virtual platforms for maximum simulation speed
• Connecting virtual platforms for a full electronics digital twin

• Delivering binary equivalence while mapping multiple architecture types to server processors
• Ensuring mixed criticality freedom from interference
• Integration with existing cloud and on-prem flows

• What are Electronics Digital Twins?
• Use cases and requirements
• Deployment in the clouds

• Virtualization as a Driver for Automotive Transformation
• Application in Smart Cockpit HPC Project
• Technological Solution

Discover a solution which enables both technology and design inovation while retaining key system attributes: cost reduction, high levels of safety, reliability, availability and performance.

• Open-Source HW for Automotive

RISC-V is disrupting the semiconductor landscape, and specifically the automotive market. In the software-defined era, system integrators are intrigued by the chance to increase innovation, agility and customization, while cutting cost and reducing supply chain insecurity. Quintauris was founded to accelerate the adoption of RISC-V globally by enabling solutions for different industries, with an initial focus in Automotive. In this session, Quintauris will present the current RISC-V automotive landscape,  the benefits RISC-V offers to the automotive industry, plus how Quintauris is already working to secure that RISC-V becomes the open standard which the semiconductor industry will based its next generation by nurturing the existing ecosystem and securing the commercial opportunities. 

• Harmonizing Standards for the Future of Software Defined Vehicles
• Collaborative Synergy: The SDV Alliance‘s Unified Vision for Software Defined Vehicles

• Collaboration: interdependencies between hardware and software (vendors) and key aspects for successful system integration
• Technology: comparison of (software) separation technologies and how they impact system security

This presentation will start with a short overview of the security implications the Software-Defined Vehicle brings to the industry. We will present our recommendation on how to address these issues on a technical level and within the supply-chain. On the latter we will outline the importance of collaboration when choosing the right SoC vendor and/or OS or middleware provider – including an industry example for a system solution. On the technical level the presentation will compare different separation technologies and their impact on attack surfaces, ECU consolidation and system performance.

• Open-source software in safety-related functions
• Linux usage in safety-related applications

• What lies beyond AUTOSAR

The performance controllers of Software-Defined Vehicles (SDVs) feature robust operating systems, which are either Linux-based or commercial off-the-shelf real-time operating systems. The current standard for the middleware used between applications and operating systems is AUTOSAR Adaptive. Despite continuous development since its initial release in March 2017, Original Equipment Manufacturers (OEMs) and Tier-1 suppliers have had to address its shortcomings to meet their specific requirements. Consequently, software architecture design and integration have become exceedingly complex and laborious, leading to high costs. The approach of in-house development ("Corporate OS") has consumed substantial resources and finances, yet it has failed to produce any distinctive products. As a result, the industry is in search of a widely available, comprehensive solution to the middleware challenge. This presentation outlines the various challenges, both functional and non-functional, and offers potential pathways to a sustainable solution, with a view towards programs slated for production by 2030.

• Optimizing use of coherent and non-coherent NoCs
• Physically-aware NoC design
• Functionally safe NoC architectures

This presentation will illustrate the challenges and solutions of data-transport architectures for automotive artificial intelligence (AI), Advanced Driver Assistance Systems (ADAS), and embedded vision architectures and discuss implementation aspects for Networks-on-Chips (NoCs) for System-on-Chips and Systems of Chiplets. Advanced EE architectures, especially in the context of AI, ADAS, and Embedded Vision applications, present unique challenges in data transport architectures to procure all relevant data from DRAMs and efficiently store and transport them in on-chip caches to allow efficient computing. These challenges directly translate into specific requirements for NoC implementation, impacting performance, power consumption, and cost, efficiently addressing the challenges posed by what the industry calls the "memory wall" – the much faster improvement of processor vs. DRAM memory access speed. In addition, for the automotive application domain, developers must consider safety and resilience to allow for ISO26262 and related certifications, which we will address in detail.